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[Other resource] SystemC片上系统设计源代码

Description: SystemC片上系统设计的源代码： 书籍介绍： SystemC是被实践证明的优秀的系统设计描述语言，它能够完成从系统到门级、从软件到硬件、从设计到验证的全部描述。SystemC 2.01已作为一个稳定的版本提交到IEEE，申请国际标准。 本书为配合清华大学电子工程系SystemC相关课程的教学而编写。全书分9章，内容包括：硬件描述语言的发展史；SystemC出现的历史背景和片上系统设计方法学概述；SystemC的基本语法；SystemC的寄存器传输级设计和SystemC的可综合语言子集，以及根据作者设计经历归结的RTL设计准则和经验；接口、端口和通道等SystemC行为建模实例——片上总线系统；SystemC与VHDL/Verilog HDL的比较；SystemC的验证标准和验证方法学；SystemC开发工具SystemC_win、WaveViewer等，以及使用MATLAB进行SystemC算法模块的验证。每一章都精心编写了课后习题以配合教学的需要。 本书可作为大学电子设计自动化（EDA）相关课程教材，也可供电子工程技术人员作为SystemC设计、应用开发的技术参考书。本书丰富的实例源代码特别适合初学者根据内容实际运行、体会，举一反三，以掌握SystemC进行应用系统设计。 -SystemC system on chip design source : books introduced : SystemC has been proven in practice is an excellent system design description language, it can be completed from the system level to the door, from hardware to software, from design to verification of all description. SystemC has 2.01 as a stable version submitted to the IEEE, the application of international standards. The book to tie in electronic engineering at Tsinghua University SystemC related courses and preparation of teaching. Book nine chapters, including : hardware description language development history; SystemC is the historical background and system-on-chip design methodology outlined; SystemC basic grammar; SystemC register-transfer-level design and synthesis of SystemC language subset, as well as design experience b
Platform: | Size: 2640735 | Author: c.li | Hits:

[USB develop] USB2_chip

Description: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Platform: | Size: 36519 | Author: 戴鹏 | Hits:

[Other resource] verilog_ise_spatan3_clock

Description: verilog 时钟程序实例在ise下编译通过spatan3的芯片-Verilog clock procedures and ideally under the examples compiled by the chip spatan3
Platform: | Size: 459263 | Author: wanglei | Hits:

[Other resource] AUDIO_DAC

Description: 一个关于声音处理的Verilog语言编写的解码芯片，可以用于FPGA处理芯片的IP核，欢迎大家来用。-a voice on the Verilog language decoder chip, FPGA can be used to handle IP core chips, all are welcome to use.
Platform: | Size: 2009 | Author: 赵春生 | Hits:

[Other resource] DE2_TV

Description: 一个模拟视频输入转VGA视频输出的Verilog程序，视频解码芯片采用ADV7181B，VGA DAC采用ADV7123，强力推荐-an analog video input to VGA video output Verilog procedures, Video decoder chip used ADV7181B, VGA DAC used ADV7123, strongly recommended!
Platform: | Size: 26953 | Author: 李全 | Hits:

[Other resource] Verilogexample

Description: Verilog.pdf。有Verilog的大量范例。适合于想动手设计芯片的人。-Verilog.pdf. Verilog is a large number of examples. Suited to fight in the chip design.
Platform: | Size: 113864 | Author: 苗权 | Hits:

[Other resource] NumClock

Description: 基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计• 测试• 实验》课程中多功能数字钟实验所要求的所有功能和其它一些扩展功能。包括：基本功能——以数字形式显示时、分、秒的时间，小时计数器为同步24进制，可手动校时、校分；扩展功能——仿广播电台正点报时，任意时刻闹钟（选做），自动报整点时数（选做）；其它扩展功能——显示年月日（能处理大月小月，可手动任意设置年月日），秒表（包括开始、暂停和清零）。-based Altera FPGA series (Cyclone EP1C3T144C8) , Verilog HDL, MAX7219 Digital Display chips, 4x4 matrix keyboard, TDA2822 chip power amplifier and loudspeakers of the "Electronic Circuit Design
Platform: | Size: 23375 | Author: 田世坤 | Hits:

[Other resource] cmos_FPGA

Description: 采用Verilog语言,实现了FPGA控制视频芯片的数据采集,并将数据按帧存储起来-Verilog language, to achieve control of the FPGA chip video data acquisition, Data will be stored up by frame
Platform: | Size: 1592 | Author: margie | Hits:

[Embeded-SCM Develop] echo_dj

Description: verilog写的回波抵消程序，相当于写了个回波抵消的芯片，不是dsp，可编译后下载于FPGA,绝对原创，写了很长时间。-Verilog echo canceller written procedures, wrote the equivalent of echo canceller chip, not dsp, can be downloaded from the compiled FPGA, absolute originality, writing for a long time.
Platform: | Size: 4629 | Author: 丁谨 | Hits:

[Other resource] s_fifo

Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench
Platform: | Size: 2279 | Author: 彭帅 | Hits:

[Other resource] uart_verilog

Description: 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
Platform: | Size: 9682 | Author: 施向东 | Hits:

[Other resource] fpga1394

Description: 这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.-This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.
Platform: | Size: 3394 | Author: 吴才路 | Hits:

[VHDL-FPGA-Verilog] fpga1394

Description: 这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.-This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.
Platform: | Size: 3072 | Author: 吴才路 | Hits:

[VHDL-FPGA-Verilog] ad73311

Description: AD73311芯片的控制和数据程序，用于控制音频AD芯片。(AD73311 chip control and data program)
Platform: | Size: 5120 | Author: fengyuanzyt | Hits:

[VHDL-FPGA-Verilog] ambo2000

Description: AMBE2000芯片的控制，和编码方式控制，码率的控制，成熟的可配置的控制模块。(AMBE2000 chip control and coding control, rate control, mature and configurable control module.)
Platform: | Size: 8192 | Author: fengyuanzyt | Hits:

[VHDL-FPGA-Verilog] FPGA_实时时钟设计

Description: 通过配置DS1302芯片来实现实时时钟的监测，我们通过通过控制2个按键来选择我们要在数码管上显示的时间，按下按键1我们来显示周几，按下按键2来显示年月日，不按显示时分秒，这样显示复合我们的数字表的显示(By configuring DS1302 chip to monitor the real-time clock, we select the time that we want to display on the digital tube by controlling 2 keys. Press key 1 to show the week, press the key 2 to show the year and month, not according to the display time, so that the display of the display of the display of our digital table.)
Platform: | Size: 356352 | Author: 硅渣渣 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FPGA片内FIFO实例，对FPGA片内FIFO进行读写测试(FPGA FIFO example, reading and writing FIFO in FPGA chip.)
Platform: | Size: 3554304 | Author: 小猪仔521 | Hits:

[VHDL-FPGA-Verilog] sram_sp_hse_8kx8

Description: SRAM 8K*8 芯片存储器 芯片存储器 芯片存储器(SRAM 8K*8 Chip memory Chip memory)
Platform: | Size: 3072 | Author: 1234556 去啊 | Hits:

[VHDL-FPGA-Verilog] NoC Verilog Codes

Description: Network on Chip design using XY routing algorithm with FPGA implementation (Verilog)
Platform: | Size: 7777 | Author: gsrwork2017@gmail.com | Hits:

[Other] Verilog高级数字系统设计技术与实例分析

Description: Serial link systems have gradually dominated over parallel link systems in modern high-speed data link communications. The use of differential signal serial communications prolongs the length of the data transmission channels, which parallel communications can not match due to the signal degradation effects caused by, for example, crosstalk among parallel link wires. In addition, the maximum tolerable skew among the parallel link wires limits their maximum allowable data transmission speed. This chapter provides an introduction to serial link systems and also gives an outline of the thesis, which is devoted to the development of single chip, high-speed, serial link communications techniques for multi-channel and multi-standard applications.
Platform: | Size: 23811196 | Author: 61219131@qq.com | Hits:
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